This invention relates generally to digital circuit design in a test and emulation environment and more particularly to reducing hardware complexity and inefficiency in supporting a memory subsystem with memories of differing speeds by using a programmable counter to support memory accesses.
A memory subsystem of a microprocessor based system is usually comprised of more than a single type of memory and it is not unusual for the memory subsystem to be built from a multitude of memory types. For example, there is often an extremely fast register based memory, a very fast cache memory, and at least one type of relatively fast random access memory (RAM) memory. Each type of memory can have a different access time, i.e., a time period required to read a data value from or write a data value to an address in the memory. The access time is typically defined as a time duration between initiation of the read or write access and when a result from the read or write access is valid. Should the system attempt to use the data before the access time expires, the data used may not be match up with what is actually in the memory and validity of the data is not ensured. The access time of a memory is often referred to as memory speed and a common way to describe the memory speed is to specify a number of wait-states required for memory access. A wait-state is a cycle of a clock driving the memory subsystem, a fast memory will have a small number of wait-states (or even zero wait-states), while a slow memory will have a large number of wait-states.
In the system with more than one type of memory, there must be some control logic to ensure that memory accesses to the different types of memories wait the required number of wait-states associated with each type of memory to ensure validity of the data. While it is certainly possible to wait the longest number of wait-states for every memory access, it is also the least efficient way to do so. In certain situations, the amount of logic required to support a memory subsystem with memories of varying speed can be crucial. For example, in a testing and emulating environment, additional logic must be kept to a minimum since any additional logic adds extra gates and devices that can themselves be faulty and cause functionality problems, i.e., the additional logic added to support the testing and emulating of the memory subsystem have themselves become faulty and cause the system to be faulty or at least appear to be faulty. Therefore, any additional logic must be minimized.
Some previous testing and emulating systems have had to include a separate set of logic for each type of memory in the system. This is inefficient and introduces a large amount of additional hardware. In an effort to minimize added logic, designers of other systems have chosen to simply test and emulate only one type of memory, such as the fast register memory or fast scratch RAM, e.g., portions of the memory subsystem lying within a microprocessor, and leave the responsibility of the testing and emulating of the remaining portions of the memory subsystem to the user. However, by moving the testing and emulating tasks squarely onto the shoulders of the user, the designers of the system are relying on the diligence of the user. This may result in the memory subsystems that are not fully tested. A need has therefore arisen for a testing and emulating system that can test and emulate all types of memories in the microprocessor based system and at the same time introduces a minimum amount of additional logic and complexity to the microprocessor based system.
In one aspect, the present invention provides an apparatus that supports testing and emulating a memory subsystem within a microprocessor based system comprising a data input for inputting data and memory addresses, a data output for outputting data, a programmable counter, a signal line, a program memory interface, and a test circuit. The test circuit further comprising an instruction register scan chain, at least one data register scan chain, and a finite state machine controlling the operation of the instruction register scan chain and the data register scan chains.
The present invention has a principal advantage in that it can support any arbitrary number of different memory speeds with a single set of logic, therefore greatly reducing the complexity of the apparatus. The minimal complexity of the invention and the fact that the complexity remains constant with the number of different memories supported allows the inclusion of the present invention into a design without significantly impacting the reliability or the overall size of the design itself.
An additional advantage of the present invention is its ability to support many different memory speeds, i.e., its great flexibility. This allows for a large amount of freedom in the application of the apparatus, permitting its installation in many different environments with minimal modifications to the apparatus"" design.